In IC chip design, there is an ever-increasing push to have a higher number and density of devices, such as transistors, packed inside an IC chip. However, having a higher number and density of devices requires that the IC chip have more “interconnects” as well. The number and importance of interconnects are increasing, due to such factors as timing and noise effects, as the size of devices on the IC chip become smaller. An interconnect is generally defined as a pathway for signals to travel between devices within an IC chip, such as a Very Large Scale Integrated (“VLSI”) chip. These interconnects introduce problems into circuits of the IC chip, such as timing mismatches, unfavorably affecting the signal to noise ratio, through the creation of parasitics. These problems must be addressed in the design process of the IC chip.
IC chip designers therefore perform many simulations of the IC chip, such as the VLSI chip, under various input conditions, to check the flow of the signals through the interconnections of the IC chip. These simulations help determine the performance of the circuits in the IC chip and are of prime importance in designing circuits that are best suited and most competitive for a given technology. A VLSI chip, for instance, typically has hundreds of millions of transistors and a similarly large number of interconnects between the transistors. Therefore, the VLSI chip needs a great number of signal flow simulations and variation of parameters to properly model VLSI chip behavior. The analysis of these interconnects has become ever more important, and will become even more so as the density of IC chips continues to increase.
However, the currently available IC chip simulators are unable to handle very large networks comprising resistive and capacitive (“RC”) nodes without using excessive computing resources, such as memory and CPU time, while still being able to give an accurate description of a signal flow at an arbitrary input frequency through the RC networks of the IC chip. This inability is of concern, as it causes delays in the ability to bring an IC chip to market. Furthermore, in order to have faster IC chip design and marketing, it is also desired that the IC simulator handle incremental changes to the simulated RC networks, without the necessity of re-simulating the transfer function for the entire RC network. The seriousness of the problem can be gauged by the fact that the IC chip designers may need to perform millions of simulations on these interconnects to get accurate results.
Some tools have been developed to perform interconnect simulation of IC chips. The interconnects are modeled as the resistance and capacitance values of RC nodes (“nodes”). Generally, while various simulation tools are acceptable for certain specific uses, they all have their disadvantages. While some simulation tools perform an acceptable analysis of an input signal propagation through the RC networks of an IC chip, these simulation tools are prohibitively expensive in terms of time and memory required for the simulation. Therefore, these simulation tools cannot be used for the simulation and analysis of large systems of RC networks of IC chips in an acceptable timeframe.
On the other hand, there are simulation tools which are fast and use less memory, but they are not accurate enough to meet demands of the current and future technologies. These simulation tools are generally based on techniques for the reduction of the transfer function of the RC network to a simpler mathematical model. Some examples of such reduction tools are Rapid Interconnect Circuit Evaluation (“RICE”) and Asymptotic Waveform Evaluation (“AWE”). Hence, if a particular node of the RC network changes its characteristics, the reduction of the entire RC network needs to be performed again. For example, if the resistance or capacitance of a particular node are modified, the entire simulated RC network must be recalculated. Further, the reduction of the network is based on the single frequency characteristics of the input signal, not a plurality of potentially desired input signals.
Some general purpose circuit simulation tools do exist, such as SPICE™ and ACES™ that try to optimize speed, memory usage, and accuracy. However, these general purpose circuit simulation tools are too generic, and therefore do not focus exclusively on RC network analysis, such as is found when simulating IC chips. The tools also fail to deliver the necessary processing capacity in a timely and efficient manner. Accordingly, these general purpose circuit simulations fail to provide practical solutions for designing IC chips.
Therefore, there is a need for an RC network simulator that overcomes the shortcomings of existing simulators.